MAX10 pin too close to PLL clock

Here is the error cause, could you read this link?

http://sw-web.altera.com/tools/quartuskit/16.0/current.linux64/linux64/quartus/common/help/webhelp/index.htm#msgs/msgs/efiomgr_output_too_close_to_pll_clock_input.htm

Use another pll ref_clk input, or create clock from other pll, or change the error target pin location.

I don't think all IO standard user IOs are prohibited adjacent to PLL clk in, I gues some IOs are restricted due to affection of switching noise.