We have only SPI interface available on host CPU. Looking to understand how the CPU can do CRAM configuration or update the CFM/UFM internal flash in MAX10 with the interface. Most document using QSPI but to interface to SPI Flash, not host. Can the QSPI controller run stand-alone to update the CRAM or CFM without NIOS. I have the RPD file created. The file is created from pof file. 1. How to create .rbf (raw binary file)? 2. Is remote update (RSU) supported for MAX10? The IP Catalog does not highlight that for MAX10 in Quartus 18.1 std. Did Intel replace RSU with NIOS now? 3. What IP needed at MAX10 side to receive the RPD file - UART, I2C or can Slave SPI work. Most of the documents and application notes are about using NIOS. However this require software. Looking for how the MAX10 can received data purely together hardware connection only.

Hi,MAX 10 FPGA does support Remote System Upgrade feature. You may like to refer to the following document on options available to do this. https://www.intel.com/content/www/us/en/programmable/documentation/sss1393988509894.html#sss1394717031728It also provide links to a RSU example. It is also possible to access RSU block through user logic, which in your case will be based on SPI interface (link provided in above document).Please note that CFM/UFM requires a .pof file.Regards

I looked at that before submitting questions. In Quartus, platform designer DOES NOT highlight “remote Update IntelFPGA IP” under the IP Catalog Configuration and Programming for selection if MAX10 selected as device. The section 3.5 (Accessing Remote System Upgrade through User Logic” too light to understand in depth of anything. If there are reference design or application note beyond helps. The RSU example provided is for UART with NIOS based RSU and not with user logic (no NIOS). Maybe you can point me to the RSU example of USER LOGIC. Thanks.

looked at that before submitting questions. In Quartus, platform designer DOES NOT highlight “remote Update IntelFPGA IP” under the IP Catalog Configuration and Programming for selection if MAX10 selected as device. See the attached file that says "altera_remote_update" not supported for Max10 family. The section 3.5 (Accessing Remote System Upgrade through User Logic” too light to understand in depth of anything. If there are reference design or application note beyond helps. The RSU example provided is for UART with NIOS based RSU and not with user logic (no NIOS). Maybe you can point me to the RSU example of USER LOGIC. Thanks.

Hello Ash, I wonder if you can help me. My goal is to implement RSU on a max 10 device via the easiest method. My FPGA design is is all discreet logic, manually written in VHDL, I have no Nios implementation and have no experience with Nios. Until now, I have created my design in Quartus 18.1 using only manually written VHDL, and programmed a pof to the device each time via usb blaster. Could you recommend an approach for somebody like me, and any examples that might help? Kind regards AT

Max10 CRAM configuration with RPD file via system console/host CPU

6 Replies

Ash_R_Intel
Regular Contributor
4 years ago
Hi,
MAX 10 FPGA does support Remote System Upgrade feature. You may like to refer to the following document on options available to do this.
https://www.intel.com/content/www/us/en/programmable/documentation/sss1393988509894.html#sss1394717031728
It also provide links to a RSU example. It is also possible to access RSU block through user logic, which in your case will be based on SPI interface (link provided in above document).

Please note that CFM/UFM requires a .pof file.

Regards
- GD76
  Occasional Contributor
  4 years ago
  I looked at that before submitting questions.
  
  In Quartus, platform designer DOES NOT highlight “remote Update IntelFPGA IP” under the IP Catalog Configuration and Programming for selection if MAX10 selected as device.
  
  The section 3.5 (Accessing Remote System Upgrade through User Logic” too light to understand in depth of anything. If there are reference design or application note beyond helps.
  
  The RSU example provided is for UART with NIOS based RSU and not with user logic (no NIOS).
  
  Maybe you can point me to the RSU example of USER LOGIC.
  
  Thanks.
- GD76
  Occasional Contributor
  4 years ago
  
  looked at that before submitting questions.
  
  In Quartus, platform designer DOES NOT highlight “remote Update IntelFPGA IP” under the IP Catalog Configuration and Programming for selection if MAX10 selected as device.
  
  See the attached file that says "altera_remote_update" not supported for Max10 family.
  
  The section 3.5 (Accessing Remote System Upgrade through User Logic” too light to understand in depth of anything. If there are reference design or application note beyond helps. The RSU example provided is for UART with NIOS based RSU and not with user logic (no NIOS).
  
  Maybe you can point me to the RSU example of USER LOGIC.
  
  Thanks.
- atattyman
  New Contributor
  4 years ago
  Hello Ash,
  
  I wonder if you can help me. My goal is to implement RSU on a max 10 device via the easiest method.
  
  My FPGA design is is all discreet logic, manually written in VHDL, I have no Nios implementation and have no experience with Nios.
  
  Until now, I have created my design in Quartus 18.1 using only manually written VHDL, and programmed a pof to the device each time via usb blaster.
  
  Could you recommend an approach for somebody like me, and any examples that might help?
  
  Kind regards
  
  AT
GD76
Occasional Contributor
4 years ago
I looked at that before submitting questions.

In Quartus, platform designer DOES NOT highlight “remote Update IntelFPGA IP” under the IP Catalog Configuration and Programming for selection if MAX10 selected as device.

The section 3.5 (Accessing Remote System Upgrade through User Logic” too light to understand in depth of anything. If there are reference design or application note beyond helps.

The RSU example provided is for UART with NIOS based RSU and not with user logic (no NIOS).

Maybe you can point me to the RSU example of USER LOGIC.

Thanks.
- jozephka99
  Contributor
  4 years ago
  If you are using 10M02 family or SC subfamily you cannot use dual configuration features. If don't you can refer: https://community.intel.com/t5/Programmable-Devices/MAX10-RSU/m-p/1346476/highlight/true#M82672

Forum Discussion

Max10 CRAM configuration with RPD file via system console/host CPU

6 Replies

Recent Discussions

Does altering the FPGA IO standard actually change something in hardware?

Stratix 10 GX Transceiver IO pairs

Debugging the FPGAs connected in passive serial mode

MegaWizard Plug-In Manager : ALTPLL [Corrupted in Quartus Prime Lite 25.1]

LTC Connector DE10-Standard FPGA