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GD76's avatar
GD76
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Max10 CRAM configuration with RPD file via system console/host CPU

We have only SPI interface available on host CPU. Looking to understand how the CPU can do CRAM configuration or update the CFM/UFM internal flash in MAX10 with the interface. Most document using QSP...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

MAX 10 FPGA does support Remote System Upgrade feature. You may like to refer to the following document on options available to do this.

https://www.intel.com/content/www/us/en/programmable/documentation/sss1393988509894.html#sss1394717031728

It also provide links to a RSU example. It is also possible to access RSU block through user logic, which in your case will be based on SPI interface (link provided in above document).


Please note that CFM/UFM requires a .pof file.


Regards


  • GD76's avatar
    GD76
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    I looked at that before submitting questions.

    In Quartus, platform designer DOES NOT highlight “remote Update IntelFPGA IP” under the IP Catalog Configuration and Programming for selection if MAX10 selected as device.

    The section 3.5 (Accessing Remote System Upgrade through User Logic” too light to understand in depth of anything. If there are reference design or application note beyond helps.

    The RSU example provided is for UART with NIOS based RSU and not with user logic (no NIOS).

    Maybe you can point me to the RSU example of USER LOGIC.

    Thanks.

  • GD76's avatar
    GD76
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    looked at that before submitting questions.

    In Quartus, platform designer DOES NOT highlight “remote Update IntelFPGA IP” under the IP Catalog Configuration and Programming for selection if MAX10 selected as device.

    See the attached file that says "altera_remote_update" not supported for Max10 family.

    The section 3.5 (Accessing Remote System Upgrade through User Logic” too light to understand in depth of anything. If there are reference design or application note beyond helps. The RSU example provided is for UART with NIOS based RSU and not with user logic (no NIOS).

    Maybe you can point me to the RSU example of USER LOGIC.

    Thanks.

  • atattyman's avatar
    atattyman
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hello Ash,

    I wonder if you can help me. My goal is to implement RSU on a max 10 device via the easiest method.

    My FPGA design is is all discreet logic, manually written in VHDL, I have no Nios implementation and have no experience with Nios.

    Until now, I have created my design in Quartus 18.1 using only manually written VHDL, and programmed a pof to the device each time via usb blaster.

    Could you recommend an approach for somebody like me, and any examples that might help?

    Kind regards

    AT