Max v cpld dpll

MAX V effectively is MAX II, with identical specification and core structure, and minimal changes, extending Z (zero power) to higher densities and introducing new packages. Rated number of programming cycles has been gracefully increased from 100 to 1000 for the UFM.

MAX II/V has an internal RC oscillator, required for operation of the internal flash and also exposed to user logic. It's not programmable. No new clock processing features are provided according to the datasheet.

The DPLL point is interesting indeed. It still written on the MAX V product page.

http://www.altera.com/products/devices/cpld/max-v/mxv-index.jsp

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...features including:

Digital PLLs (DPLLs), which enable flexible implementation of designs requiring frequency multiplication or phase shifting

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It's also written in the MAX V solution sheet http://www.altera.com/literature/po/ss-maxv-cplds.pdf

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MAX V Silicon Features and Benefits

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Phase-locked loops (PLLs) - Digital PLL implementation provides flexible implementation for designs needing frequency multiplication or phase shifting.

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So either the "clock network" chapter has been forgotten in the MAX V datasheet, or the feature has been previously planned but wasn't implemented, or it has been implemented, but doesn't work.

The DPLL feature on MAX V devices is interesting. However, the overview page has this note:

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Note:

1. Digital PLL is an optional intellectual property (IP) that can be instantiated into unused LEs.

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So is it just an IP feature? No specific silicon support? If that is the case, then why it is specific and restricted to MAX V?

Hi All,

Thanks for chiming in. How does the "instantiating optional IP" generally work with the A devices? Is it one within Quartus, like Megacore function maybe??

With X devices it is done by Coregen. But Coregen is restricted to FPGAs only not for the Coolrunner-II CPLDs.

thanks

Ananth

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the overview page has this note

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Where did you read this?

Generally, MAX II as well as MAX V are small SRAM based FPGAs rather classical CPLDs, the device core is almost identical to Cyclone III, but it lacks internal RAM, hardware PLLs and some interface types. In so far, the prerequisites to create a PLL in LEs would be the same for Cyclone or MAX II/V devices. In the above quoted document a functionality similar to the dedicated hardware PLLs of Cyclone and Stratix FPGA is described (e.g. allowing frequency multiplication and phase shifting). It can't be done will discrete time PLLs, that are suitable for low output frequencies at a fraction of the input clock only.

There's a principle method to implement a PLL in ASIC gates respectively FPGA logic cells by utilizing programmable delay line oscillators. German company Chip Cologne has filed a patent for it and is selling it as an ASIC IP.

http://www.colognechip.com/asic/ip-cores/digicc-pll-techn.pdf

But it seems unlikely, that this technique has been intended for the said MAX V PLLs.

As expectable, Altera Quartus V10.1 does not provide a DPLL Megafunction for MAX V.

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Where did you read this?

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As I said, it is in the Max V overview page:

http://www.altera.com/products/devices/cpld/max-v/overview/mxv-overview.html

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In the above quoted document a functionality similar to the dedicated hardware PLLs of Cyclone and Stratix FPGA is described (e.g. allowing frequency multiplication and phase shifting). It can't be done will discrete time PLLs, that are suitable for low output frequencies at a fraction of the input clock only.

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I agree. But the fact is that Altera is claiming it is an IP, and Altera documentation doesn't mention, so far, any silicon support. So something seems wrong, but we don't really know exactly what.

Thank you, for some reason, I didn't look back to the left side of the devices page.

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Altera documentation doesn't mention, so far, any silicon support

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Furthermore, the MAX V chip layout shown in the device manual is identical to MAX II. So there's effectively no room for it.

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So something seems wrong, but we don't really know exactly what.

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Yes. Of course a MAX V PLL would be an interesting feature. So let's wait for a clarification.

The MAX V device handbook is presently updated, but V1.1 still misses a clarification about the anounced "Digital PLL" feature. The term is listed as a pdf keyword for the document, but can't be found anywhere.

I also noticed, that the MAX V CPLD Architecture page locates a Digital PLL in the oscillator block, which sounds reasonable.

http://www.altera.com/products/devices/cpld/max-v/overview/architecture/mxv-architecture.html

I filed a service request asking for a clarification.

I have also noticed the same info.

The problem is i need a quickly ask to this question.

Does someone that has already used MAXV tell us if there is (or not) that misterious DPLL.

Furthermore i think to be urgent an explanation on this point by the ALTERA support.

Thanks to all.

The problem has been that urgent for me, because I'm not planning to use MAX V for a concrete product now, thus I didn't ask before. Getting no answer yet after three days, suggests that my question couldn't answered by the support stuff on their own.

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So my simple question is: What's are the presently available and planned clock processing features of MAX V? Will a digital PLL be available and what's the specification?

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Actually, this isn't surprizing at all, otherwise Altera marketing had put an end to the curious show before.

Perhaps you should ask your local FAE or distributors technical staff in the same regard.