Max v cpld dpll

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Where did you read this?

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As I said, it is in the Max V overview page:

http://www.altera.com/products/devices/cpld/max-v/overview/mxv-overview.html

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In the above quoted document a functionality similar to the dedicated hardware PLLs of Cyclone and Stratix FPGA is described (e.g. allowing frequency multiplication and phase shifting). It can't be done will discrete time PLLs, that are suitable for low output frequencies at a fraction of the input clock only.

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I agree. But the fact is that Altera is claiming it is an IP, and Altera documentation doesn't mention, so far, any silicon support. So something seems wrong, but we don't really know exactly what.