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Where did you read this?
Generally, MAX II as well as MAX V are small SRAM based FPGAs rather classical CPLDs, the device core is almost identical to Cyclone III, but it lacks internal RAM, hardware PLLs and some interface types. In so far, the prerequisites to create a PLL in LEs would be the same for Cyclone or MAX II/V devices. In the above quoted document a functionality similar to the dedicated hardware PLLs of Cyclone and Stratix FPGA is described (e.g. allowing frequency multiplication and phase shifting). It can't be done will discrete time PLLs, that are suitable for low output frequencies at a fraction of the input clock only.
There's a principle method to implement a PLL in ASIC gates respectively FPGA logic cells by utilizing programmable delay line oscillators. German company Chip Cologne has filed a patent for it and is selling it as an ASIC IP.
http://www.colognechip.com/asic/ip-cores/digicc-pll-techn.pdf But it seems unlikely, that this technique has been intended for the said MAX V PLLs.
As expectable, Altera Quartus V10.1 does
not provide a DPLL Megafunction for MAX V.
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