Max v cpld dpll

Thank you, for some reason, I didn't look back to the left side of the devices page.

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Altera documentation doesn't mention, so far, any silicon support

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Furthermore, the MAX V chip layout shown in the device manual is identical to MAX II. So there's effectively no room for it.

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So something seems wrong, but we don't really know exactly what.

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Yes. Of course a MAX V PLL would be an interesting feature. So let's wait for a clarification.