Honored Contributor
Honored ContributorMAX V effectively is MAX II, with identical specification and core structure, and minimal changes, extending Z (zero power) to higher densities and introducing new packages. Rated number of programming cycles has been gracefully increased from 100 to 1000 for the UFM.
MAX II/V has an internal RC oscillator, required for operation of the internal flash and also exposed to user logic. It's not programmable. No new clock processing features are provided according to the datasheet. The DPLL point is interesting indeed. It still written on the MAX V product page. http://www.altera.com/products/devices/cpld/max-v/mxv-index.jsp --- Quote Start --- ...features including: Digital PLLs (DPLLs), which enable flexible implementation of designs requiring frequency multiplication or phase shifting --- Quote End --- It's also written in the MAX V solution sheet http://www.altera.com/literature/po/ss-maxv-cplds.pdf --- Quote Start --- MAX V Silicon Features and Benefits ... Phase-locked loops (PLLs) - Digital PLL implementation provides flexible implementation for designs needing frequency multiplication or phase shifting. --- Quote End --- So either the "clock network" chapter has been forgotten in the MAX V datasheet, or the feature has been previously planned but wasn't implemented, or it has been implemented, but doesn't work.
New ContributorIs there anywhere I find information on the number of PLL available the operating frequency range and the loop filter time constant. There seem to be a lot information about the MAX V chips, next nothing on the DPLL's and the possible configurations. Are there any pdf files I can look at with this information in?
