MAX V - UFM IP core signals remain undefined when I try to simulate using a test bench

I have implemented a system where I store a 3 bit value to the UFM in my CPLD using a 'SET' signal, and read that value from the UFM using a 'GET' signal.

The system is running on the board partly (Enough to know the UFM is storing data and responding to read signal - using LEDs), but when I simulate using a testbench on modelsim - all the signals going into UFM and coming out is undefined. All the other signals are working fine.

Using MAX V CPLD
- Quartus Prime

- Modelsim

Do I need to include any UFM IP core library to my TB file? If so, please let me know how to do that?

Warnings:
- ** Warning: (vsim-3473) Component instance "ufm_parallel_0 : UFM_Config_ufm_parallel_0" is not bound.

- ** Warning: (vsim-8684) No drivers exist on out port /ufm_tb/UUT/ufm_inst/data_valid, and its initial value is not used.

- ** Warning: (vsim-8684) No drivers exist on out port /ufm_tb/UUT/ufm_inst/dataout, and its initial value is not used

- ** Warning: (vsim-8684) No drivers exist on out port /ufm_tb/UUT/ufm_inst/nbusy, and its initial value is not used.

It would be a great help.

Thanks

VR_S