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VR_S's avatar
VR_S
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3 years ago

MAX V - UFM IP core signals remain undefined when I try to simulate using a test bench

I have implemented a system where I store a 3 bit value to the UFM in my CPLD using a 'SET' signal, and read that value from the UFM using a 'GET' signal. The system is running on the board partly...
IntelSupport's avatar
IntelSupport
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3 years ago

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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