max operational Frequency

Assuming that you're using the "Classic Timing Analyser" (I'm not sure if this applies to Time Quest), go to Processing >> Compilation Report.

Expand the "Timing Analyser" bit and it will show you what has failed - click on the specific parameter to show you the nets.

Yes, these two critical paths will determine your maximum operational frequency.

There are various places you can dinf the Fmax - continuing from above, if you click Timing Analyser >> Summary then you can see there. If you click Timing Analyser >> Clock Setup (or hold) then it will help you work out which paths in particular are a problem.

Don't set your Fmax requirement to be much higher than it needs to be - it will make life unnecessarily hard for the place and route.

Hope this helps

Yes batfink, you helped me, thanks.

But I want to clarify the following: What does that means that my design don't meet timing requirements? Is there any compilation parameters regarding the clock settings that is set by default and they are the main reason why my design don't meet timing requirements ?

Looking at timing report I can see three various times: Worst-case tsu, th and tco? What is the meaning of these timing parameters? :confused:

tsu - setup time

tco - clock to output time

tpd - propagation delay

th - hold time

fmax - maximum frequency at which the design will have to work at.

If you read the Quartus help there's a lot more information about this stuff.

If you set values for these requirements (Assignments >> Timing Analysis Settings >>Classic Timing Analyser Settings), then the place and route will work to try and meet them. If it can't meet them then it will tell you.

It is then up to you to change the design or add constraints - then try another compilation and see how you get on.

What timing requirements are not being met?

The parameter which don't work is tpd. I also don't have any information about fmax (in timing report).

I saw, using your advice about setting timing parameters, that there is no any constraint about timing parameters and clock frequency. Still my design don't meet timing requirements.

By the way, I saw that design works good after programming FPGA at f=50MHz clock.

If you don't set a timing requirement then success / failure won't be reported. You should still what that timing is though (e.g. if you haven't set fmax then you won't get a message saying that fmax hasn't been read but if you look in the report it should still tell you what it is).

What have you set tpd to? How close to meeting it are you?

If you only narrowly miss the tpd requirement then you might be able to add some placement constraints to help the fitter (you'll need to read up on that). If you're quite a way off then you'll probably have to change your design.

Batfink,

I just want to see which is maximal operational frequency for my design. Which is the way to do it? Since I don't know the meaning of tco,th and tsu, how can I set them? So, in classic timing analyzer setting I did not set any value: tpd nor th nor tsu nor tco neither fmax.

Which value should I set to these parameters to see maximal possible clock frequency for my desing? I have only one clock signal named clock.

Thank you very much for your explanations and sorry for bothering you.

Best regards,

Bojan

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I just want to see which is maximal operational frequency for my design. Which is the way to do it?

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Processing >> Compilation Report >> Timing Analyser >> Summary

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Since I don't know the meaning of tco,th and tsu, how can I set them?

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If you read the Quartus help there's a lot more information about this stuff. You may not need to set them - it depends on your design.

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Which value should I set to these parameters to see maximal possible clock frequency for my desing?

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The timing settings will be determined by your design. The fitter will place and route your design and try and meet these settings. I think you need to read up on this subject - it's too big a subject for a forum really. If you set the fmax to be a lot higher than you really need then you can overconstraint the design and make it more difficult for the fitter to meet timing requirements - give it realistic requirements.

If you haven't set any timing requirements I'm not quite sure why you are getting the message that your design doesn't meet timing requirements.

OK Batfink,

I think you have a right, it is too big stuff for the forum.

In the meantime I've read about QuartusII timing analysis and realized some facts. Thank you very much for helping me. ;)

Bojan

Hi All

i've some problems with time analyzer. i use Quartus 11 and when i wanna compile my project, in compilation report\timing analyzer there are no reports (something like inactive) and for example in clock section "co clock to report" shows, so i cannt see the fmax of my project can anybody help me?

thanks