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Altera_Forum
Honored Contributor
Honored Contributormax operational Frequency
Hello folks, I use Quartus II 8.1 and DE2 board. When I compile my design I don't have errors in report, only warnings. But, looking at the report window I can see that my design don't meet t...
Altera_ForumHonored Contributor
Honored ContributorThe parameter which don't work is tpd. I also don't have any information about fmax (in timing report).
I saw, using your advice about setting timing parameters, that there is no any constraint about timing parameters and clock frequency. Still my design don't meet timing requirements. By the way, I saw that design works good after programming FPGA at f=50MHz clock.
