tsu - setup time
tco - clock to output time
tpd - propagation delay
th - hold time
fmax - maximum frequency at which the design will have to work at.
If you read the Quartus help there's a lot more information about this stuff.
If you set values for these requirements (Assignments >> Timing Analysis Settings >>Classic Timing Analyser Settings), then the place and route will work to try and meet them. If it can't meet them then it will tell you.
It is then up to you to change the design or add constraints - then try another compilation and see how you get on.
What timing requirements are not being met?