max Clock rate at GPIO? (DE2 Board)

This concerns to timing specifications of Cyclone II device EP2C35F672C6.

According the I/O standard used you can calculate maximum delays and clock rate for every FPGA's pin. http://www.altera.com/literature/hb/cyc2/cyc2_cii51005.pdf

One design i've done used the EP2C70F672I8 with 64MHz IO clock speeed.

The spi with 25MHz spiclock was no problem.

SDRam with 96MHz also functional within industrial enviroment.

Could you please explain a bit more what you mean with

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But when I select a to high Baud rate, the other side seems to not get all bits.

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What is a high Baud rate for you ?

have you had a look at the signal waveform ?

do you have voltage over/undershots ?

how did you setup quartus ?

did you use registered outputs, specify slew rate, output current, fast input / output register ?

Thanks for the answers.

Now I know its not the DE2 Board. It's the other side.