Forum Discussion

Altera_Forum

Honored Contributor

14 years ago

mapping a port to several signals

Hi all!

I have got an issue, I don't really know if it's a bug from ModelSi or an error from my code.

Maybe soeone will be able to tell me...

A/° I am using:

--- Quote Start ---

ModelSim DE 6.6a

Revision: 2010.03

Date: Mar 19 2010

--- Quote End ---

B/° This code works:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
end entity test;
architecture behavioural of test is
    
    component foo
    port
    (
        s : out std_logic_vector(31 downto 0)
    );
    end component foo;
    
    constant K : natural range 1 to 31 := 15;
    
    signal msb : std_logic_vector(31 downto K);
    signal lsb : std_logic_vector((K - 1) downto 0);
    
begin
    
    foo_inst : foo
    port map
    (
        s(31 downto K)      => msb,
        s((K - 1) downto 0) => lsb
    );
    
end architecture behavioural;

--- Quote Start ---

ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd

# Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package numeric_std

# -- Compiling entity test

# -- Compiling architecture behavioural of test

ModelSim>

--- Quote End ---

C/° I tried to replace the constant K with e generic that I can set when starting the simulation, but it does not work

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
    generic
    (
        K : natural range 1 to 31 := 15
    );
end entity test;
architecture behavioural of test is
    
    component foo
    port
    (
        s : out std_logic_vector(31 downto 0)
    );
    end component foo;
    
    signal msb : std_logic_vector(31 downto K);
    signal lsb : std_logic_vector((K - 1) downto 0);
    
begin
    
    foo_inst : foo
    port map
    (
        s(31 downto K)      => msb,
        s((K - 1) downto 0) => lsb
    );
    
end architecture behavioural;

--- Quote Start ---

ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd

# Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package numeric_std

# -- Compiling entity test

# -- Compiling architecture behavioural of test

# ** Error: /home/reinauld/Bureau/test.vhd(29): (vcom-1024) Individually associated formal "s" must be identified with a locally static name.

# ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1024) Individually associated formal "s" must be identified with a locally static name.

# ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1048) Non-locally static choice (association# 2, choice# 1) is allowed only if it is the only choice of the only association.

# ** Error: /home/reinauld/Bureau/test.vhd(33): VHDL Compiler exiting

# /opt/modelsim_de/modelsim_dlx/linuxpe/vcom failed.

ModelSim>

--- Quote End ---

Can anyone comment this? Maybe suggest another way to achieve what I try to do?

The point is to map output of a signal driver (that reads stimuli from a file) to several stimuli signals.

Thanks,

Julien

16 Replies

Altera_Forum
Honored Contributor
14 years ago
Still, ModelSim is not consistent

Slices with indexes that are not static:
- are not allowed in port mapping
- BUT are allowed in continuous affectations (in this case, if slices are wrong, the code compiles but the simulation crashes with an error message during load)

The following examples illustrate this: they are perfectly identical from a functional point of view, but one compiles and the other does not.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is generic ( K : natural range 1 to 31 := 15 ); end entity test; architecture behavioural of test is component foo port ( s : out std_logic_vector(31 downto 0) ); end component foo; signal msb : std_logic_vector(31 downto K); signal lsb : std_logic_vector((K - 1) downto 0); begin foo_inst : foo port map ( s(31 downto K) => msb, s((K - 1) downto 0) => lsb ); end architecture behavioural;

--- Quote Start ---
ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd
# Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity test
# -- Compiling architecture behavioural of test
# ** Error: /home/reinauld/Bureau/test.vhd(29): (vcom-1024) Individually associated formal "s" must be identified with a locally static name.
# ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1024) Individually associated formal "s" must be identified with a locally static name.
# ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1048) Non-locally static choice (association# 2, choice# 1) is allowed only if it is the only choice of the only association.
# ** Error: /home/reinauld/Bureau/test.vhd(33): VHDL Compiler exiting
ModelSim>
--- Quote End ---

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is generic ( K : natural range 1 to 31 := 15 ); end entity test; architecture behavioural of test is component foo port ( s : out std_logic_vector(31 downto 0) ); end component foo; signal sig : std_logic_vector(31 downto 0); signal msb : std_logic_vector(31 downto K); signal lsb : std_logic_vector((K - 1) downto 0); begin foo_inst : foo port map ( s => sig ); msb <= sig(31 downto K); lsb <= sig((K - 1) downto 0); end architecture behavioural;

--- Quote Start ---
ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd
# Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity test
# -- Compiling architecture behavioural of test
ModelSim>
--- Quote End ---

Is there a reason?
Altera_Forum
Honored Contributor
14 years ago
@kaz

The code I proposed is for illustration only, it has no purpose.

However you can imagine a testbench that generates stimuli from a file, instanciate a DUT, and checks outputs of the DUT in a process, reporting errors whenever they occur.

This testbench would be an entity with no port, but with a generic for the stimuli file name for instance (in order to be able to run various scenarios without recompiling the testbench each time) --> just as in my example code.

Also, it would instanciate a module as stimuli driver. This module would read the stimuli file and drive an 'out' signal accordingly. So basically this module would have only an 'out' port --> just as in my example code.
(In that case, the driver would have the same generic as the testbench, and the generic would be propagated from the bench to the driver. But since this has nothing to do with my concern, so it was not necessary to my example code)
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

Is there a reason?
--- Quote End ---

yes. It will be part of the VHDL LRM that port maps have to be static but signal assignments dont need to be.
Altera_Forum
Honored Contributor
14 years ago
And do you know the reason for that?
Altera_Forum
Honored Contributor
14 years ago
Because rules are rules!! Dont question the LRM. ;)

from the '93 LRM, section 1.1.1.2 Ports, line 94:
"The actual, if a port or signal, must be denoted by a static name. The actual, if an expression, must be a globally static expression"
Altera_Forum
Honored Contributor
14 years ago
Ok then ;)

Forum Discussion

mapping a port to several signals

16 Replies

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