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Altera_Forum's avatar
Altera_Forum
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14 years ago

mapping a port to several signals

Hi all! I have got an issue, I don't really know if it's a bug from ModelSi or an error from my code. Maybe soeone will be able to tell me... A/° I am using: --- Quote Start --...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Is there a reason?

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yes. It will be part of the VHDL LRM that port maps have to be static but signal assignments dont need to be.