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Honored Contributor
Honored Contributormapping a port to several signals
Hi all! I have got an issue, I don't really know if it's a bug from ModelSi or an error from my code. Maybe soeone will be able to tell me... A/° I am using: --- Quote Start --...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Is there a reason? --- Quote End --- yes. It will be part of the VHDL LRM that port maps have to be static but signal assignments dont need to be.
