mapping a port to several signals

@kaz

The code I proposed is for illustration only, it has no purpose.

However you can imagine a testbench that generates stimuli from a file, instanciate a DUT, and checks outputs of the DUT in a process, reporting errors whenever they occur.

This testbench would be an entity with no port, but with a generic for the stimuli file name for instance (in order to be able to run various scenarios without recompiling the testbench each time) --> just as in my example code.

Also, it would instanciate a module as stimuli driver. This module would read the stimuli file and drive an 'out' signal accordingly. So basically this module would have only an 'out' port --> just as in my example code.

(In that case, the driver would have the same generic as the testbench, and the generic would be propagated from the bench to the driver. But since this has nothing to do with my concern, so it was not necessary to my example code)