mapping a port to several signals

Still, ModelSim is not consistent

Slices with indexes that are not static:

- are not allowed in port mapping

- BUT are allowed in continuous affectations (in this case, if slices are wrong, the code compiles but the simulation crashes with an error message during load)

The following examples illustrate this: they are perfectly identical from a functional point of view, but one compiles and the other does not.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
    generic
    (
        K : natural range 1 to 31 := 15
    );
end entity test;
architecture behavioural of test is
    
    component foo
    port
    (
        s : out std_logic_vector(31 downto 0)
    );
    end component foo;
    
    signal msb : std_logic_vector(31 downto K);
    signal lsb : std_logic_vector((K - 1) downto 0);
    
begin
    
    foo_inst : foo
    port map
    (
        s(31 downto K)      => msb,
        s((K - 1) downto 0) => lsb
    );
    
end architecture behavioural;

--- Quote Start ---

ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd

# Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package numeric_std

# -- Compiling entity test

# -- Compiling architecture behavioural of test

# ** Error: /home/reinauld/Bureau/test.vhd(29): (vcom-1024) Individually associated formal "s" must be identified with a locally static name.

# ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1024) Individually associated formal "s" must be identified with a locally static name.

# ** Error: /home/reinauld/Bureau/test.vhd(30): (vcom-1048) Non-locally static choice (association# 2, choice# 1) is allowed only if it is the only choice of the only association.

# ** Error: /home/reinauld/Bureau/test.vhd(33): VHDL Compiler exiting

ModelSim>

--- Quote End ---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
    generic
    (
        K : natural range 1 to 31 := 15
    );
end entity test;
architecture behavioural of test is
    
    component foo
    port
    (
        s : out std_logic_vector(31 downto 0)
    );
    end component foo;
    signal sig : std_logic_vector(31 downto 0);
    
    signal msb : std_logic_vector(31 downto K);
    signal lsb : std_logic_vector((K - 1) downto 0);
    
begin
    
    foo_inst : foo
    port map
    (
        s => sig
    );
    
    msb <= sig(31 downto K);
    lsb <= sig((K - 1) downto 0);
    
end architecture behavioural;

--- Quote Start ---

ModelSim> vcom -reportprogress 300 -work work /home/reinauld/Bureau/test.vhd

# Model Technology ModelSim DE vcom 6.6a Compiler 2010.03 Mar 19 2010

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package numeric_std

# -- Compiling entity test

# -- Compiling architecture behavioural of test

ModelSim>

--- Quote End ---

Is there a reason?