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akhilesh_sreedharan's avatar
akhilesh_sreedharan
Icon for New Contributor rankNew Contributor
9 days ago

M9K utilization is different for the same RAM IP for two different projects.

I have a single-port Altera Avalon on-chip memory of 18,432 bytes with a data width of 32-bit instantiated in the two different QSYS subsystem used in different projects.

The first project consumes 18 M9K blocks for this memory IP as shown below. This seems correct since, each M9K has about 1 kB of memory, so 18kB of memory should consume about 18 M9K blocks.

Project 1 with lower RAM utilization

For, the same-IP the second project consumes 32 M9K blocks instead of 18 as shown in the image below:

Project 2 with higher RAM utilization

The settings for the RAM-IP are as shown in the image below:

Quartus Tool Version : Quartus 18.1 Standard

FPGA Device : MAX-10 10M50DAF256I7G

Please help us understand why the same RAM IPs have different utilization for different projects. Also, what settings can be made to the second project so that it consumes only 18 M9K blocks.

Thank you,

Akhilesh.

Configuration
Programmable Logic Device

2 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    4 days ago

    Quartus Standard 18.1 is relatively old. Is it possible to try the latest Quartus Standard 25.1 and check if the issue persists?
    Please archive the project before migrating to the newer Quartus version.
    If the issue still occurs, could you share both project .QAR files so I can investigate further?

    Regards,
    Richard Tan

    • akhilesh_sreedharan's avatar
      akhilesh_sreedharan
      Icon for New Contributor rankNew Contributor
      1 hour ago

      Thank you for replying to my query!

      Since, the project has a NIOS-II core I couldn't build it using Quartus 25.1 std. However, I did build the project using Quartus 23.1.1 std and the resource utilization numbers are still the same ( 18 M9k - Project 1, 32M9K - Project 2). 

      Due to confidentiality reasons I cannot share the .QAR files. Further, I tried inspecting the synthesis and fitter logs in detail. It was observed that the project 1 which consumes lower RAM blocks (18) has the following logs in its synthesis report:

      Info (270021): Converted the following 4 logical RAM block slices to smaller depth
	Info (270020): Converted the following logical RAM block "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ALTSYNCRAM" slices to smaller maximum block depth of 1024
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a5"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a4"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a1"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a0"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a3"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a2"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a15"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a14"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a11"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a13"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a16"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a12"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a21"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a30"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a29"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a28"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a27"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a26"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a25"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a10"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a24"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a9"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a23"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a8"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a22"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a7"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a6"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a20"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a19"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a18"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a17"
		Info (270019): RAM block slice "QSYS:qsys_inst|QSYS_onchip_memory2_0:onchip_memory2_0|altsyncram:the_altsyncram|altsyncram_llc1:auto_generated|ram_block1a31"

      This particular entry is not present in the second project that consumes 32 M9K cells. Is this something that could be related to this issue ? 

      - Akhilesh S.