Occasional ContributorCould you please provide the information?
The link in the LVDS SERDES Intel® FPGA IP User Guide (section I/O Timing Analysis)
Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer, Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook
doesn't work.
Thanks
Jens
Super ContributorHi,
most likely you are using an outdated IP user guide release.
I try most recent version 2022.09.20 https://www.intel.com/content/www/us/en/docs/programmable/683520/22-1-20-0-1.html and the link works for me. https://www.intel.com/content/www/us/en/docs/programmable/683461/
As you are apparently working with Arria 10 GX I would suggest to locate the basic Arria 10 GX documentation.
Occasional ContributorHi,
thanks for your answer.
Yes, technically the link you mentioned above may work. In terms of content, however, it makes no sense! There is nothing about assigning timing.
When I hit on the link in the document you referred above I get an error message.
Super ContributorHi,
I see. Dead links in user guides etc. are experienced quite often.
I find the respective paragraph about "Assigning input delay" in 2016 Arria 10 handbook under Timing and Optimization for Arria 10 Devices (5.6.7. in recent versions):
Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer
To obtain the RSKM value, assign an appropriate input delay to the LVDS receiver from the TimeQuest Timing Analyzer constraints menu.
1. On the menu in the TimeQuest Timing Analyzer, select Constraints > Set Input Delay.
2. In the Set Input Delay window, select the desired clock using the pull-down menu. The clock name must reference the source synchronous clock that feeds the LVDS receiver.
3. Click the Browse button (next to the Targets field).
4. In the Name Finder window, click List to view a list of all available ports. Select the LVDS receiver serial input ports according to the input delay you set, and click OK.
5. In the Set Input Delay window, set the appropriate values in the Input delay options and Delay value fields.
6. Click Run to incorporate these values in the TimeQuest Timing Analyzer.
7. Repeat from step 1 to assign the appropriate delay for all the LVDS receiver input ports. If you have already assigned Input Delay and you need to add more delay to that input port, turn on the Add Delay option.
It has been removed in later handbook revisions, e.g. of 2020. Obvious problem is that links in newer LVDS IP handbook revisions still refer to obsolete paragraph. Question is why it has been removed. I guess that respective sdc contraints are generated in Quartus Pro automatically.
Occasional ContributorHi FvM,
Yes, indeed! Thanks but I have noticed that in DPA-FIFO mode the Timing Analyzer does not perform static I/O timing
analysis. So this constraints are not needed?
BR
Jens
Regular ContributorHi Jens,
Yes, you are correct. In the user guide it was mentioned that the Timing Analyzer does not perform static I/O timing analysis for soft-CDR and DPA-FIFO mode.
