Forum Discussion
Jens
Occasional Contributor
Occasional ContributorLVDS SERDES Intel® FPGA IP User Guide
Could you please provide the information? The link in the LVDS SERDES Intel® FPGA IP User Guide (section I/O Timing Analysis) Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer,...
FvM
Super Contributor
Super ContributorHi,
most likely you are using an outdated IP user guide release.
I try most recent version 2022.09.20 https://www.intel.com/content/www/us/en/docs/programmable/683520/22-1-20-0-1.html and the link works for me. https://www.intel.com/content/www/us/en/docs/programmable/683461/
As you are apparently working with Arria 10 GX I would suggest to locate the basic Arria 10 GX documentation.
JensOccasional Contributor
Occasional ContributorHi,
thanks for your answer.
Yes, technically the link you mentioned above may work. In terms of content, however, it makes no sense! There is nothing about assigning timing.
When I hit on the link in the document you referred above I get an error message.
