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Jens
Occasional Contributor
Occasional ContributorLVDS SERDES Intel® FPGA IP User Guide
Could you please provide the information? The link in the LVDS SERDES Intel® FPGA IP User Guide (section I/O Timing Analysis) Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer,...
JensOccasional Contributor
Occasional ContributorHi FvM,
Yes, indeed! Thanks but I have noticed that in DPA-FIFO mode the Timing Analyzer does not perform static I/O timing
analysis. So this constraints are not needed?
BR
Jens
