Forum Discussion
Jens
Occasional Contributor
Occasional ContributorLVDS SERDES Intel® FPGA IP User Guide
Could you please provide the information? The link in the LVDS SERDES Intel® FPGA IP User Guide (section I/O Timing Analysis) Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer,...
AqidAyman_Altera
Regular Contributor
Regular ContributorHi Jens,
Yes, you are correct. In the user guide it was mentioned that the Timing Analyzer does not perform static I/O timing analysis for soft-CDR and DPA-FIFO mode.
