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Altera_Forum's avatar
Altera_Forum
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16 years ago

LVDS interconnect

Hi all

I designed a board, There are two FPGAs, One is ep1agx50 , anothers is ep2s130. About 6 months ago, I can transmit data form ep2s130 to ep1agx50 through LVDS, But now, The ep1agx50 can't receive any correct data. I checked the schematic, and found that ep2s130 PLL－ENA pin left float, Is it reason?

Thanks forward.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The Stratix II device handbook clarifies, that PLL_ENA must be connected to GND, if not used in your design.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    PS: Clock frequency : 100Mhz, deser factor : 1, bus width : 8