LVDS input Clock Pin

ADC_CLK_D_PO has to be on a dedicated clock pin. Where do you have it assigned? Does it work if you let it float?

It's a Clock in LVDS. It's on a DIFFIO pin (P & N, so two pin). I didn't find DIFFIO clock pin!?

Do you have a location assignment on that input port? The altlvds instantiates a PLL, and there are dedicated clock portsthat must be used to drive the PLLs, i.e. it can't be any LVDS input location. If you do have it assigned, just disable that assignment and see if it fits, i.e. if Quartus can find a valid location. If so, then you need to find one that matches your board layout.

Ok so our board has a problem... Our LVDS clock is not routed on a DIFFCLK pin.

Or can I use the altddio_in to read the ADC? (it accept my LVDS DIFFIO clock as inclock).

Assuming your DCLK (coming from the ADC) goes to a (C)DPCLK pin, using altddio_in is a perfect way to do this. The DCLK is 90 degrees in respect to the data and the frame signal, so you don't need a PLL. Quartus II might have a hard time fitting it in a Cyclone IV speed-grade 8L when running the ADC at the higher frequencies, esp. 65 MHz.

Is the clock rate 65MHz? That might be do-able without a PLL. The altlvds automatically adds a PLL, which requires a dedicated clock pin. If you instantiate the altddio_in megafunctions, you can drive those directly. On alterawiki.com I have a document on source-synchronous timing:

At 65 MHz input clock the ADC generates a 445 MHz output clock with only 240 ps setup and hold time on it DDR data output signals.