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Honored Contributor
Honored ContributorLVDS input Clock Pin
Hi, I'm using an ADC AFE5808 from TI with LVDS output. I use a Cyclone IV EP4CE75F23I8L and the mega function Altlvds_rx. I configure the rx_inclock pin ADC_CLK_D_P as LVDS pin with his ...
Altera_ForumHonored Contributor
Honored ContributorIs the clock rate 65MHz? That might be do-able without a PLL. The altlvds automatically adds a PLL, which requires a dedicated clock pin. If you instantiate the altddio_in megafunctions, you can drive those directly. On alterawiki.com I have a document on source-synchronous timing:
http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest There are some basic sample designs you can use, although you'll need to remove the PLL. There are even some TI examples.
