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Honored Contributor
Honored ContributorLVDS input Clock Pin
Hi, I'm using an ADC AFE5808 from TI with LVDS output. I use a Cyclone IV EP4CE75F23I8L and the mega function Altlvds_rx. I configure the rx_inclock pin ADC_CLK_D_P as LVDS pin with his ...
Altera_ForumHonored Contributor
Honored ContributorAssuming your DCLK (coming from the ADC) goes to a (C)DPCLK pin, using altddio_in is a perfect way to do this. The DCLK is 90 degrees in respect to the data and the frame signal, so you don't need a PLL. Quartus II might have a hard time fitting it in a Cyclone IV speed-grade 8L when running the ADC at the higher frequencies, esp. 65 MHz.
