LVDS input Clock Pin

Assuming your DCLK (coming from the ADC) goes to a (C)DPCLK pin, using altddio_in is a perfect way to do this. The DCLK is 90 degrees in respect to the data and the frame signal, so you don't need a PLL. Quartus II might have a hard time fitting it in a Cyclone IV speed-grade 8L when running the ADC at the higher frequencies, esp. 65 MHz.