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sbj's avatar
sbj
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2 months ago

LVDS Compatibility with GTS Refclk (CML / HCSL)

We are evaluating a use case where an LVDS clock source drives a GTS transceiver reference clock input, which is typically configured for CML or HCSL standards.   Is this usage supported, particula...
Core Logic
Programmable Logic Device
sbj's avatar
sbj
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2 months ago

Hi, 

is there a way to find out what pin configurations and electrical considerations (e.g., termination, biasing) are required to ensure proper operation?

Just some general documentation to have a better overview of what is inside the fpga and what needs to be added externally, would be very helpful.

 

Thanks

Ash_R_Altera's avatar
Ash_R_Altera
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1 month ago

Kindly confirm whether the suggested steps have addressed your concern.
 

Regards

  • sbj's avatar
    sbj
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    1 month ago

    All good. Thank you