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sbj's avatar
sbj
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2 months ago

LVDS Compatibility with GTS Refclk (CML / HCSL)

We are evaluating a use case where an LVDS clock source drives a GTS transceiver reference clock input, which is typically configured for CML or HCSL standards.   Is this usage supported, particula...
Core Logic
Programmable Logic Device
sbj's avatar
sbj
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2 months ago

Hi, 

is there a way to find out what pin configurations and electrical considerations (e.g., termination, biasing) are required to ensure proper operation?

Just some general documentation to have a better overview of what is inside the fpga and what needs to be added externally, would be very helpful.

 

Thanks

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Hi,

    Please refer to the diagram in the following link showing the receiver buffer of Agilex 5 GTS. It shows Con-chip which is inside the FPGA and also Con-board, which user is supposed to put on the board.

    https://docs.altera.com/r/docs/817660/26.1/gts-transceiver-phy-user-guide/receiver-buffer-and-equalizer

     

    As mentioned earlier, you may use the development kit as a reference. We recommend you to do a board level simulation to make sure that the signal integrity on the board design is good. 

     

    Regards,

    Altera Support

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Kindly confirm whether the suggested steps have addressed your concern.
     

    Regards

    • sbj's avatar
      sbj
      Icon for New Contributor rankNew Contributor
      1 month ago

      All good. Thank you