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sbj's avatar
sbj
Icon for New Contributor rankNew Contributor
2 months ago

LVDS Compatibility with GTS Refclk (CML / HCSL)

We are evaluating a use case where an LVDS clock source drives a GTS transceiver reference clock input, which is typically configured for CML or HCSL standards.   Is this usage supported, particula...
Core Logic
Programmable Logic Device
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
2 months ago

Hi,

In most high speed interface cases, the FPGA refclk pin is configured with CML IO standard to interface with the LVDS driver. HCSL is typically used in PCIe interfaces.

 

You can very well take the devkit as a reference to interface LVDS clock driver to GTS transceiver. It uses 0.1uF of AC coupling to adjust the common-mode voltage conflict. The termination (parallel 100 ohm) closer to the receiver set the correct bias.

 

Hope this helps.

 

Regards