LVDS clock lines and data lines left right problem

Question

Background: I have to interface an ADC board that was designed to interface with Xilinx FPGA but now the requirement is to interface with a stratix 4. So the ADC board was not designed keeping stratix 4GX in mind.

There is one clock and 8 output LVDS channels. 6 channels are connected to Bank5, 1 channel is connected to bank6 and the last one is connected to bank2. clock is going to AB6. Problem is that i cant connect the 8th channel, which is connected to bank2, to the deserializer. Lot of errors pop up. (Left and right side problem i suppose) What i understand is that the clock coming in AB6 pin cannot deserialize the bank6 lvds channel.

Anybody faced this issue before? Is there any patch that i can put in the constraints file to avoid this error? Half of my brain has burnt out. Please help the other half from burning.

Solutions, suggestions and recommendations are highly appreciated.

altera_forum · Answer

Edit ::"" AB6 pin cannot deserialize the bank2 lvds channel.""

altera_forum · Answer

I haven't looked at the layout, but you're right that high-speed IO serdes use dedicated circuitry, including dedicated clock channels from the PLL that only drive IO on its side of the device. This allows for lower skew and much high frequency operation, but is less flexible. This is a physical restriction in the silicon, not just the software.

What's the clock rate and is it DDR? If it's not too fast, you might be able to use a global clock tree, which can drive all I/O, but has less performance.

altera_forum · Answer

Thanks Rysc:

It is DDR and 1120Mbps per channel

Can you help me out on the global clock tree solution?

I think i need to have a dedicated external clock coming to the bank2 (left side) of the FPGA too. Right?

That is currently not possible... hmmmmm

altera_forum · Answer

So a 560MHz clock? It naturally depends on how much skew there is from the transmitter, but my first assumption is that it should work. Take a look at the document and sample projects here:

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest

altera_forum · Answer

Yes 560MHz clock. I will try the global clock option and let me go through the document.  Meanwhile any shortcuts are welcome.

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LVDS clock lines and data lines left right problem

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