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Altera_Forum
Honored Contributor
Honored ContributorLVDS clock lines and data lines left right problem
Background: I have to interface an ADC board that was designed to interface with Xilinx FPGA but now the requirement is to interface with a stratix 4. So the ADC board was not designed keeping strat...
Altera_ForumHonored Contributor
Honored ContributorSo a 560MHz clock? It naturally depends on how much skew there is from the transmitter, but my first assumption is that it should work. Take a look at the document and sample projects here:
http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest
