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Altera_Forum
Honored Contributor
Honored ContributorLVDS clock lines and data lines left right problem
Background: I have to interface an ADC board that was designed to interface with Xilinx FPGA but now the requirement is to interface with a stratix 4. So the ADC board was not designed keeping strat...
Altera_ForumHonored Contributor
Honored ContributorYes 560MHz clock. I will try the global clock option and let me go through the document.
Meanwhile any shortcuts are welcome.
