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Altera_Forum's avatar
Altera_Forum
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13 years ago

LVDS clock lines and data lines left right problem

Background: I have to interface an ADC board that was designed to interface with Xilinx FPGA but now the requirement is to interface with a stratix 4. So the ADC board was not designed keeping strat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I haven't looked at the layout, but you're right that high-speed IO serdes use dedicated circuitry, including dedicated clock channels from the PLL that only drive IO on its side of the device. This allows for lower skew and much high frequency operation, but is less flexible. This is a physical restriction in the silicon, not just the software.

What's the clock rate and is it DDR? If it's not too fast, you might be able to use a global clock tree, which can drive all I/O, but has less performance.