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Altera_Forum's avatar
Altera_Forum
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13 years ago

LVDS clock lines and data lines left right problem

Background: I have to interface an ADC board that was designed to interface with Xilinx FPGA but now the requirement is to interface with a stratix 4. So the ADC board was not designed keeping strat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks Rysc:

It is DDR and 1120Mbps per channel

Can you help me out on the global clock tree solution?

I think i need to have a dedicated external clock coming to the bank2 (left side) of the FPGA too. Right?

That is currently not possible... hmmmmm