Forum Discussion
Honored ContributorLoss of lock in the PLL of ALTLVDS_Rx
Hi,
I have two similar boards based on Cyclone III. My project works in both boards. This project performs exchange of data between boards with LVDS (physical link is made by SATA cable and connectors). Two boards are connected by two SATA cables. Accidentally (it may be very sparse), I see the loss of lock in the PLL of ALTLVDS_Rx (I capture falling edge of output "rx_locked"). What can be the reason of it ?23 Replies
Altera_ForumInstead of cascading of PLLs, I changed clock generator. Now it is Jauch O 10,0-JO75-B-3,3-2-T1-LF. Its phase jitter < 1 ps and frequency stability is 50 ppm. Previous generator (Golledge, GXO-7531) had 50 ppm and its phase jitter was unknown, I think it was very bad as manufacturer didn't publish it.
After continuous hard test (during 3 days) it was only one loss of lock !!! It is amazing result.- Altera_Forum
Creating ALTLVDS_Rx with external PLL is time-taking procedure for my project (it is necessary to rewrite several finite state machines related to ALTLVDS_Rx). I'll do it during some days.
And I have one more idea about PLL of ALTLVDS_Tx. After compilation there is critical warning: PLL"altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component|lvds_tx_7ki1:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_90". To compensate tx_inclock of ALTLVDS_Tx I have decided to cascade main PLL of my project and PLL of ALTLVDS_Tx. Namely, I created one more clock output "clk_lvds" (20 MHz) in main PLL and reconfigured main PLL in source-syncronous mode with compensated clock "clk_lvds". This new clock "clk_lvds" feeds input "tx_inclock" in ALTLVDS_Tx. After compilation the warning appeared: PLL"altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component|lvds_tx_7ki1:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input. And attached to warning info message: Input port INCLK[0] of node "altlvds_tx0:inst23|altlvds_tx:altlvds_tx_component|lvds_tx_7ki1:auto_generated|lvds_tx_pll" is driven by altpll0:inst38|altpll:altpll_component|altpll_67s2:auto_generated|clk[3]~clkctrl which is OUTCLK output port of Clock control block type node altpll0:inst38|altpll:altpll_component|altpll_67s2:auto_generated|clk[3]~clkctrl. I see, there is no cascading of PLLs. How can I do it? Thanks. - Altera_Forum
You can try. But I don't know if it actually helps with the "loss of lock" issue. It's just following the hardware manual suggestion.
- Altera_Forum
Yes,
it is impossible with internal PLL of ALTLVDS_Rx/Tx. I need to create ALTLVDS_Rx with option "Use external PLL" turned on. Is it what you recommend? - Altera_Forum
It would be used in manual instantiation of an altpll component, which is my preferred method to place a PLL. Using the ALTPLL MegaFunction through the Wizard, it's an advanced PLL parameter, as you described above. It's not available with an "internal" ALT_LVDS PLL, I think.
- Altera_Forum
Ok, thank you.
I'm sorry, how can I get access to the generic map of the RX-PLL instance? - Altera_Forum
The suggestion is to set bandwidth_type => "HIGH" instead of bandwidth_type => "AUTO" in the generic map of the RX-PLL instance.
- Altera_Forum
PLL settings in ALTLVDS_Rx:
SDC pin name: inst24|altlvds_rx_component|auto_generated|lvds_rx_pll PLL mode: Source Synchronous Compensate clock: clock0 Compensated input/output pins: lvds_data_rx, lvds_data_rx Switchover type: - Input frequency 0:20.0 MHz Input frequency 1:- Nominal PFD frequency:20.0 MHz Nominal VCO frequency:639.8 MHz VCO post scale: 2 VCO frequency control: Auto VCO phase shift step: 195 ps VCO multiply: - VCO divide: - Freq min lock: 9.8 MHz Freq max lock: 20.32 MHz M VCO Tap: 0 M Initial: 3 M value: 32 N value: 1 Charge pump current: setting 1 Loop filter resistance: setting 24 Loop filter capacitance: setting 0 Bandwidth: 450 kHz to 980 kHz Real time reconfigurable: Off Scan chain MIF file: - Preserve PLL counter order: Off PLL location: PLL_2 Inclk0 signal: lvds_clock_rx Inclk1 signal: - Inclk0 signal type: Dedicated Pin Inclk1 signal type: - - Altera_Forum
I found settings of PLL.
PLL of ALTLVDS_Tx: SDC pin name: inst23|altlvds_tx_component|auto_generated|lvds_tx_pll PLL mode: Normal Compensate clock: clock0 Compensated input/output pins: -- Switchover type: - Input frequency 0: 20.0 MHz Input frequency 1 - Nominal PFD frequency: 20.0 MHz Nominal VCO frequency: 639.8 MHz VCO post scale: 2 VCO frequency control: Auto VCO phase shift step :195 ps VCO multiply -- VCO divide -- Freq min lock: 9.8 MHz Freq max lock: 20.32 MHz M VCO Tap: 0 M Initial: 3 M value: 32 N value: 1 Charge pump current setting: 1 Loop filter resistance setting: 24 Loop filter capacitance setting: 0 Bandwidth: 450 kHz to 980 kHz Real time reconfigurable: Off Scan chain MIF file: - Preserve PLL counter order: Off PLL location: PLL_1 Inclk0 signal: clk_ext Inclk1 signal - Inclk0 signal type: Dedicated Pin Inclk1 signal type - - Altera_Forum
The PLL bandwidth is reported in the compilation report. The settings under Anlysis and synthesis, parameter settings and the actual value under Fitter/Resource Section/PLL.
