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Altera_Forum
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15 years ago

Loss of lock in the PLL of ALTLVDS_Rx

Hi, I have two similar boards based on Cyclone III. My project works in both boards. This project performs exchange of data between boards with LVDS (physical link is made by SATA cable and conn...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Instead of cascading of PLLs, I changed clock generator. Now it is Jauch O 10,0-JO75-B-3,3-2-T1-LF. Its phase jitter < 1 ps and frequency stability is 50 ppm. Previous generator (Golledge, GXO-7531) had 50 ppm and its phase jitter was unknown, I think it was very bad as manufacturer didn't publish it.

After continuous hard test (during 3 days) it was only one loss of lock !!!

It is amazing result.