Honored Contributor
Honored ContributorI found settings of PLL.
PLL of ALTLVDS_Tx: SDC pin name: inst23|altlvds_tx_component|auto_generated|lvds_tx_pll PLL mode: Normal Compensate clock: clock0 Compensated input/output pins: -- Switchover type: - Input frequency 0: 20.0 MHz Input frequency 1 - Nominal PFD frequency: 20.0 MHz Nominal VCO frequency: 639.8 MHz VCO post scale: 2 VCO frequency control: Auto VCO phase shift step :195 ps VCO multiply -- VCO divide -- Freq min lock: 9.8 MHz Freq max lock: 20.32 MHz M VCO Tap: 0 M Initial: 3 M value: 32 N value: 1 Charge pump current setting: 1 Loop filter resistance setting: 24 Loop filter capacitance setting: 0 Bandwidth: 450 kHz to 980 kHz Real time reconfigurable: Off Scan chain MIF file: - Preserve PLL counter order: Off PLL location: PLL_1 Inclk0 signal: clk_ext Inclk1 signal - Inclk0 signal type: Dedicated Pin Inclk1 signal type -
