loop must end 5000 iteration error

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i have a verilog program ,while compiling it gives error like loop must end in 5000 iteration on line 36

module memory

(mem_dump,

ntb_encoder,

enable_m,

nr_w_m,

addr_m,

din_m,

dout_m);

input mem_dump;

input ntb_encoder;

input enable_m;

input nr_w_m;

input [16:0] addr_m;

input [7:0] din_m;

output [7:0]dout_m;

reg [7:0] mem[0:131071];

reg [7:0] dout_m;

reg mem_dump_bit;

integer i;

integer p;

integer k;

integer handle1;

integer handle2;

integer handle3;

integer j;

integer l;

initial

begin: ram_initialization_block

begin

p=131072;

for (i=0; i<p; i=i+1)

mem[i]= 8'd0;

$readmemh("ref_frame.txt", mem,0,25343);

$readmemh("cur_frame.txt", mem,25344,50687);

mem_dump_bit = 1'b0;

end

end

always@(ntb_encoder or nr_w_m or enable_m or din_m or addr_m or mem_dump)

begin: memory_block

if (enable_m == 1'b0)

dout_m = 8'bZZZZZZZZ;

else if (enable_m == 1'b1 && nr_w_m == 1'b0 && ntb_encoder == 1'b1)

dout_m = mem[addr_m];

else if (enable_m == 1'b1 && nr_w_m == 1'b1 && ntb_encoder == 1'b1 && addr_m >= 50688)

mem[addr_m] = din_m;

else

dout_m = 8'bZZZZZZZZ;

if (mem_dump == 1'b1 && mem_dump_bit == 1'b0)

begin

handle1=$fopen("vertical_mv_bitstream.txt");

for (k=52272; k<53856; k=k+1)

$fdisplay(handle1,"%d",mem[k]);

$fclose(handle1);

handle2=$fopen("horizontal_mv_bitstream.txt");

for (j=50688; j<52272; j=j+1)

$fdisplay(handle2,"%d",mem[j]);

$fclose(handle2);

handle3=$fopen("res_bitstream.txt");

for (l=53856; l<79200; l=l+1)

$fdisplay(handle3,"%d",mem[l]);

$fclose(handle3);

end

end

endmodule

please any one help

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Hi,

which tool do you use ? Is a simulation your intention ?

Kind regards

GPK

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Hi,

which tool do you use ? Is a simulation your intention ?

Kind regards

GPK

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Hi,

in case of Quartus the default limit for constant verilog loops is 5000. You can change the setting under :

Assignment -> Settings -> Analysis&Synthesis -> More Settings ... -> Iteration limit for constant Verilog loops

With your large loops I would expect a long runtime for "Analysis & Synthesis".

Kind regards

GPK

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Hi,

Assignment -> Settings -> Analysis&Synthesis -> More Settings ... -> Iteration limit for constant Verilog loops

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THANK YOU!! This is exactly what I needed!

What I find curious is that the default iteration limit of 5000 only allows you to loop 4999 times rather than 5000 times like you would think. I had to loop exactly 5000 times so I had to set the limit to 5001. Seems like a simple fence-post programming error in the Quartus tool. Not a big deal though. I'm just glad they let you change the limit. :)

Hello,

To those of you looking for this option in quartus 15.1,

It has moved to Assignments / Settings / Compiler settings / Advanced Settings [= a button in the frame] / iteration limit for constant verilog loops.

Best Regards,

Johi.