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Altera_Forum's avatar
Altera_Forum
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16 years ago

loop must end 5000 iteration error

i have a verilog program ,while compiling it gives error like loop must end in 5000 iteration on line 36 module memory (mem_dump, ntb_encoder, enable_m, nr_w_m, addr_m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Hi,

Assignment -> Settings -> Analysis&Synthesis -> More Settings ... -> Iteration limit for constant Verilog loops

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THANK YOU!! This is exactly what I needed!

What I find curious is that the default iteration limit of 5000 only allows you to loop 4999 times rather than 5000 times like you would think. I had to loop exactly 5000 times so I had to set the limit to 5001. Seems like a simple fence-post programming error in the Quartus tool. Not a big deal though. I'm just glad they let you change the limit. :)