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Altera_Forum
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16 years ago

loop must end 5000 iteration error

i have a verilog program ,while compiling it gives error like loop must end in 5000 iteration on line 36 module memory (mem_dump, ntb_encoder, enable_m, nr_w_m, addr_m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hello,

To those of you looking for this option in quartus 15.1,

It has moved to Assignments / Settings / Compiler settings / Advanced Settings [= a button in the frame] / iteration limit for constant verilog loops.

Best Regards,

Johi.