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Altera_Forum
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16 years ago

loop must end 5000 iteration error

i have a verilog program ,while compiling it gives error like loop must end in 5000 iteration on line 36 module memory (mem_dump, ntb_encoder, enable_m, nr_w_m, addr_m...
Altera_Forum's avatar
Altera_Forum
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16 years ago

--- Quote Start ---

Hi,

which tool do you use ? Is a simulation your intention ?

Kind regards

GPK

--- Quote End ---

Hi,

in case of Quartus the default limit for constant verilog loops is 5000. You can change the setting under :

Assignment -> Settings -> Analysis&Synthesis -> More Settings ... -> Iteration limit for constant Verilog loops

With your large loops I would expect a long runtime for "Analysis & Synthesis".

Kind regards

GPK