LogicLocking performance improvemnets

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I have a deisgn in a 2S130 that is essentially 2 IP cores and some glue logic. With all timing switches set to maximum we can barely meet timing.

I have played around with logic locking the cores but I have not seen any performance improvement.

My question is: Would you expect a performance improvement with logic locking or does Quartus does an optimal job with a flat compile?

Several years ago I definately had to logic lock a Xilinx design because the ISE was placing some logic in odd locations resulting in timing errors.

Based on what I have seen with the Quartus 8.0 tool, logic locking reduces my compilation time but does not seem to increase performance.

Woud be interested to get some opinions on this ..

thanks

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Hi,

I assume that you have a problem with fmax. There are many aspect which you to consider in this case. Lets start with the basics.

All clocks are constraints ? All false pathes cut ? What is your device utilization ?

What is the maxium slack and how many paths are effected ? Are the violations

all in one block ?

Kind regards

GPK

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Hi,

I assume that you have a problem with fmax. There are many aspect which you to consider in this case. Lets start with the basics.

All clocks are constraints ? All false pathes cut ? What is your device utilization ?

What is the maxium slack and how many paths are effected ? Are the violations

all in one block ?

Kind regards

GPK

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The device utilization is high (91% ALMs). The main issue that nearly all the logic is from 2 IP cores that we do not have much visibility into.

Any additional timing constraints or false paths we would need to go back to the vendor and question them.

My question was more of a general one. If the FPGA is tight for timing using a flat compile, would you expect logic locking regions to have an impact? Or is it on a design by design basis?

Looking at the placement after a flat compile, Quartus seems to place the 2 cores pretty much where I would have logic locked them anyway.

I can meet timing by turning on all the timing switches and increasing placer and router effort. I don't like when designs only meet timing with maximum effort, you just know at some point another feature will be needed and you'll fail timing at the worst time.

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The device utilization is high (91% ALMs). The main issue that nearly all the logic is from 2 IP cores that we do not have much visibility into.

Any additional timing constraints or false paths we would need to go back to the vendor and question them.

My question was more of a general one. If the FPGA is tight for timing using a flat compile, would you expect logic locking regions to have an impact? Or is it on a design by design basis?

Looking at the placement after a flat compile, Quartus seems to place the 2 cores pretty much where I would have logic locked them anyway.

I can meet timing by turning on all the timing switches and increasing placer and router effort. I don't like when designs only meet timing with maximum effort, you just know at some point another feature will be needed and you'll fail timing at the worst time.

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Hi Flipper,

when you define a LogicRegion Quartus has to place AND route all members in your defined region. In case of a high resource utilization I expect that your fmax will decrease and the P&R time will increase. In your case I would recommend to skip LogicLock regions for large parts of the design.

When you reduce your timing effort did you get timing violation only in one module ?

Kind regards

GPK

I agree - In general I would not expect that you can improve your results over a flat compilation by constraining the design blocks to specific LogicLock regions. Usually Quartus II will do the best job given freedom with placement, and visability into the entire design at once. Of course if you have a team-based design or something like that, you might use regions to reserve space in the device for future development, or allocate area for each block in the design. But in your case, especially in a very full design, I wouldn't use LogicLock region constraints as an optimization tool.

I've heard that placement constraints are used more by the competition - maybe if the place and route engine doesn't do a good enough job in the first place? I know way back in Altera's APEX days, designers could improve performance by constraining blocks to certain parts of the chip. But with modern Quartus II versions, the tool does a pretty good job (like you observed), and the liklihood of improving it manually is pretty low!