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I have a deisgn in a 2S130 that is essentially 2 IP cores and some glue logic. With all timing switches set to maximum we can barely meet timing.
I have played around with logic locking the cores but I have not seen any performance improvement.
My question is: Would you expect a performance improvement with logic locking or does Quartus does an optimal job with a flat compile?
Several years ago I definately had to logic lock a Xilinx design because the ISE was placing some logic in odd locations resulting in timing errors.
Based on what I have seen with the Quartus 8.0 tool, logic locking reduces my compilation time but does not seem to increase performance.
Woud be interested to get some opinions on this ..
thanks
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Hi,
I assume that you have a problem with fmax. There are many aspect which you to consider in this case. Lets start with the basics.
All clocks are constraints ? All false pathes cut ? What is your device utilization ?
What is the maxium slack and how many paths are effected ? Are the violations
all in one block ?
Kind regards
GPK
Honored Contributor
