Honored Contributor
Honored ContributorI agree - In general I would not expect that you can improve your results over a flat compilation by constraining the design blocks to specific LogicLock regions. Usually Quartus II will do the best job given freedom with placement, and visability into the entire design at once. Of course if you have a team-based design or something like that, you might use regions to reserve space in the device for future development, or allocate area for each block in the design. But in your case, especially in a very full design, I wouldn't use LogicLock region constraints as an optimization tool.
I've heard that placement constraints are used more by the competition - maybe if the place and route engine doesn't do a good enough job in the first place? I know way back in Altera's APEX days, designers could improve performance by constraining blocks to certain parts of the chip. But with modern Quartus II versions, the tool does a pretty good job (like you observed), and the liklihood of improving it manually is pretty low!
