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The device utilization is high (91% ALMs). The main issue that nearly all the logic is from 2 IP cores that we do not have much visibility into.
Any additional timing constraints or false paths we would need to go back to the vendor and question them.
My question was more of a general one. If the FPGA is tight for timing using a flat compile, would you expect logic locking regions to have an impact? Or is it on a design by design basis?
Looking at the placement after a flat compile, Quartus seems to place the 2 cores pretty much where I would have logic locked them anyway.
I can meet timing by turning on all the timing switches and increasing placer and router effort. I don't like when designs only meet timing with maximum effort, you just know at some point another feature will be needed and you'll fail timing at the worst time.
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Hi Flipper,
when you define a LogicRegion Quartus has to place AND route all members in your defined region. In case of a high resource utilization I expect that your fmax will decrease and the P&R time will increase. In your case I would recommend to skip LogicLock regions for large parts of the design.
When you reduce your timing effort did you get timing violation only in one module ?
Kind regards
GPK
Honored Contributor
