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Hi,
I assume that you have a problem with fmax. There are many aspect which you to consider in this case. Lets start with the basics.
All clocks are constraints ? All false pathes cut ? What is your device utilization ?
What is the maxium slack and how many paths are effected ? Are the violations
all in one block ?
Kind regards
GPK
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The device utilization is high (91% ALMs). The main issue that nearly all the logic is from 2 IP cores that we do not have much visibility into.
Any additional timing constraints or false paths we would need to go back to the vendor and question them.
My question was more of a general one. If the FPGA is tight for timing using a flat compile, would you expect logic locking regions to have an impact? Or is it on a design by design basis?
Looking at the placement after a flat compile, Quartus seems to place the 2 cores pretty much where I would have logic locked them anyway.
I can meet timing by turning on all the timing switches and increasing placer and router effort. I don't like when designs only meet timing with maximum effort, you just know at some point another feature will be needed and you'll fail timing at the worst time.
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