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emrahener's avatar
emrahener
Icon for New Contributor rankNew Contributor
3 years ago

Limit PCIe speed to Gen2

Hi,

I am using Multi Channel DMA Intel® FPGA IP for PCI Express IP on a Agilex device to implement a x16 PCIe EndPoint. Due to some problems I want to change the advertised speed to Gen2 form Gen3. IP parameters does not allow me to do so. Is there a way to do so ?

Quartus Version :23.1

DEVICE :AGIB027R31B2E2VAA

Kind Regards,

Emrah ENER

Other Ips

10 Replies

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Can what IP parameter does not allow you to do so ?

    My suggestion is regenerate a new design example for pcie gen3.

    Is any printscreen that you can show to me ?


    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    I wish to follow up with you about this case.

    Do you have any further questions on this matter ?

    ​​​​​​​Else I would like to have your permission to close this forum ticket

    Regards,

    Wincent_Intel


    • emrahener's avatar
      emrahener
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi Wincent ,

      Screen shots is below. We are using MCDMA PCIe IP As you can see there is no Gen2 option. We want to limit our HW capability to Gen2 and don't want our endpoint to negotiate up to Gen3 speed. I also attached the speed options for streaming version which also don't have any Gen2 option.

      MCDA IP

      Streaming IP

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    You can generate the gen3 design example. But please ensure that you set your BIOS PCIe speed setting into gen2.

    Then suppose it will auto downgrade into the gen2 speed.


    You may check the gen speed via

    $ sudo lspci -s 01:00.0 -vv


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    I wish to follow up with you about this case.

    Do you have any further questions on this matter ?

    ​​​​​​​Else I would like to have your permission to close this forum ticket

    Regards,

    Wincent_Intel


    • emrahener's avatar
      emrahener
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      Down training is a capability which every PCIe endpoint must support. My question was related to limiting end point capability to Gen2 (Inside MCDMA PCIe IP) not limiting it from PCIe switch side. Can you please confirm that this is not possible through IP parameters or through modifying generated ip hdl files?

      • FvM's avatar
        FvM
        Icon for Super Contributor rankSuper Contributor
        3 years ago
        Hi,
        I'm pretty sure that you can achieve what you want by modifying generated IP files. The feature to limit the maximal speed of a PCIe design has a different purpose, it's there to reduce the interface clock speed or bitwidth when you don't need it. For some reason, the Agilex Gen 4 IP has no feature to configure for below Gen 3 speed. It's probably a matter of reducing the number of alternative core configuration.
        If you step through the PCIe simulation, you'll see that communication really starts at Gen 1 speed, going up to the maximal speed supported by both peer. I guess you can simply reduce the advertised speed, but I didn't look into the details.
        Regards,
        Frank
    • emrahener's avatar
      emrahener
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi Vincent,

      I have no further questions.

      Kind Regards,

      Emrah ENER

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi

    Thanks for confirming the answer

    Hence, This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences.

    Regards,

    Wincent_Intel