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emrahener's avatar
emrahener
Icon for New Contributor rankNew Contributor
3 years ago

Limit PCIe speed to Gen2

Hi, I am using Multi Channel DMA Intel® FPGA IP for PCI Express IP on a Agilex device to implement a x16 PCIe EndPoint. Due to some problems I want to change the advertised speed to Gen2 form Gen3....
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Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel


emrahener's avatar
emrahener
Icon for New Contributor rankNew Contributor
3 years ago

Hi,

Down training is a capability which every PCIe endpoint must support. My question was related to limiting end point capability to Gen2 (Inside MCDMA PCIe IP) not limiting it from PCIe switch side. Can you please confirm that this is not possible through IP parameters or through modifying generated ip hdl files?

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 years ago
    Hi,
    I'm pretty sure that you can achieve what you want by modifying generated IP files. The feature to limit the maximal speed of a PCIe design has a different purpose, it's there to reduce the interface clock speed or bitwidth when you don't need it. For some reason, the Agilex Gen 4 IP has no feature to configure for below Gen 3 speed. It's probably a matter of reducing the number of alternative core configuration.
    If you step through the PCIe simulation, you'll see that communication really starts at Gen 1 speed, going up to the maximal speed supported by both peer. I guess you can simply reduce the advertised speed, but I didn't look into the details.
    Regards,
    Frank