Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorLE and memory blocks in a cyclone
Hello,
I'm quite new in the world of the FPGA, indeed, I'm an engineer student in end-of-studies internship which is about using a FPGA. Well, I'm telling you that because I guess that you will think my question is a question of newbies :oops:. When I start studying FPGA, my teachers said that the most important characteristic of these devices is the number of Logic Elements. But during my internship, I did some architectures using IP and then, after a full compilation, I realized that the characteristic which constrained me the most is the "total memories bits". After few research, I understood this characteristic was the representation of the memories blocks (like M9K). Here come my question, what is the constitution of a memory block? is-it a very important parameter in a fpga? Example: My FPGA have 600K memories bits and 22K LE. After Quartus compilation, I realize that my architecture need 500K memories bits but only 2K LE. can i use le instead of memories block for 1 or 2 ip? I hope that I explained my problem clearly, Thank in advance, Clément.14 Replies
Altera_Forum--- Quote Start --- See the "ramstyle" attribute http://quartushelp.altera.com/14.0/mergedprojects/hdl/vhdl/vhdl_file_dir_ram.htm --- Quote End --- Thanks a lot !! That's exactly what I need.- Altera_Forum
See the "ramstyle" attribute
http://quartushelp.altera.com/14.0/mergedprojects/hdl/vhdl/vhdl_file_dir_ram.htm - Altera_Forum
But so, what do I do to store my functions with the LEs and not with the memories blocks? and vice versa?
- Altera_Forum
LEs can be used as memory, but they are far less dense than ram. So you can quickly lose all your LEs to larger rams that have timing issues. LE rams are meant for small high speed applications.
- Altera_Forum
I think is default behavior to use LEs if you run out of memory block
- Altera_Forum
Well, to resume my interrogations and to up the thread, here a new question:
If I am constrain by the memories blocks but not with the LEs, can I choose to store my functions with the LEs and not with the memories blocks? And vice versa? - Altera_Forum--- Quote Start --- Without having your design, we cannot say how to optimise it. --- Quote End --- Well, actually my question wasn't right. I just want to know if it is possible to choose between LEs and memories blocks for an IP? In fact, you didn't answer one of my first question which was : "what is the constitution of a memory block?". Indeed, I easily find the constitution of a LE on the internet : http://www.ccciss.info/ciss420/ch2/cyclone.le.png But I don't manage to find something who explain how a memory block is made. At beginning, I was thinking that memory block was LEs already assemble to form an internal memory for the FPGA. Now, it seem like I was wrong.
- Altera_Forum--- Quote Start --- Without having your design, we cannot say how to optimise it. --- Quote End --- Well, actually my question wasn't right. I just want to know if it is possible to choose between LEs and memories blocks for an IP? In fact, you didn't answer one of my first question which was : "what is the constitution of a memory block?". Indeed, I easily find the constitution of a LE on the internet : http://www.ccciss.info/ciss420/ch2/cyclone.le.png But I don't manage to find something who explain how a memory block is made. At beginning, I was thinking that memory block was LEs already assemble to form an internal memory for the FPGA. Now, it seem like I was wrong.
- Altera_Forum
Without having your design, we cannot say how to optimise it.
But if you're using the megawizard, then it should be fairly efficient already. The high utilisation is because you set it up that way. - Altera_Forum--- Quote Start --- Do you mean efficiency or utilisation? --- Quote End --- Well, actually I don't really know. To build my architecture, I just utilize 3 IP using the megawizard of Quartus and a top level to link them together. So, I guess Altera's IP use the memory efficiently. And the problem is that in my poor little test, I use 500K of the 600K memory bit of my cyclone IV, so do you think I can optimize it?
